AD9522-0 Datasheet, PDF (22/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

AD9522-0
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ns)
Figure 18. LVDS Differential Voltage Swing @ 800 MHz
Output Terminated 100 Ω Across Differential Pair
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0 10 20 30 40 50 60 70 80 90 100
TIME (ns)
Figure 19. CMOS Output with 10 pF Load @ 25 MHz
3.2
2pF LOAD
2.8
10pF
2.4
LOAD
2.0
1.6
1.2
0.8
0.4
0
0 1 2 3 4 5 6 7 8 9 10
TIME (ns)
Figure 20. CMOS Output with 2 pF and 10 pF Load @ 250 MHz
1600
1400
1200
7mA SETTING
1000
800
DEFAULT 3.5mA SETTING
600
400
200
0
0
200
400
600
800
1000
FREQUENCY (GHz)
Figure 21. LVDS Differential Voltage Swing vs. Frequency
Output Terminated 100 Ω Across Differential Pair
4.0
3.5
3.0
2pF
2.5
2.0
10pF
1.5
20pF
1.0
0.5
0
0
100
200
300
400
500
600
700
FREQUENCY (MHz)
Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 23. Internal VCO Phase Noise (Absolute), LVDS Output @ 633 MHz
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