AD9522-0 Datasheet, PDF (51/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

AD9522-0
SDA
SCL
S
SDA
SCL
S
MSB
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10
P
Figure 58. Acknowledge Bit
MSB = 0
ACKNOWLEDGE FROM
SLAVE-RECEIVER
ACKNOWLEDGE FROM
SLAVE-RECEIVER
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10
P
Figure 59. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
SDA
SCL
S
MSB = 1
ACKNOWLEDGE FROM
MASTER-RECEIVER
NO ACKNOWLEDGE
FROM
SLAVE-RECEIVER
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10
P
Figure 60. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
The no acknowledge bit is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
R/W bit is 1, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Transfer Format section.
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (8-bit) from either master (write mode) or
slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted per
transfer is unrestricted. In write mode, the first two data bytes
immediately after the slave address byte are the internal memory
(control registers) address bytes with the high address byte first.
This addressing scheme gives a memory address up to 2¹⁶ − 1 =
65,535. The data bytes after these two memory address bytes are
register data written into the control registers. In read mode, the
data bytes after the slave address byte are register data read from
the control registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10th clock pulse
following the acknowledge bit for the last data byte from the
slave device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter)
but does not pull it low during the ninth clock pulse. This is
known as a no acknowledge bit. By receiving the no acknowledge
bit, the slave device knows that the data transfer is finished and
releases the SDA line. The master then takes the data line low
during the low period before the 10th clock pulse and high
during the 10th clock pulse to assert a stop condition.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time, and partially transferred bytes are discarded.
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