AD9522-0 Datasheet, PDF (28/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

AD9522-0
REF_SEL
VS GND
RSET
REFMON
OPTIONAL
REFIN
REFIN
BYPASS
LF
REF1
REFERENCE
SWITCHOVER
REF2
STATUS
STATUS
BUF
AMP
LOW DROPOUT
REGULATOR (LDO)
DISTRIBUTION
REFERENCE
STATUS
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
ZERO DELAY BLOCK
PROGRAMMABLE
N DELAY
CLK
CLK
PD
SYNC
RESET
EEPROM
DIVIDE BY 1,
2, 3, 4, 5, OR 6
10
DIGITAL
LOGIC
EEPROM
DIVIDE BY
1 TO 32
SP1
SERIAL
PORT
SP0
DECODE
SCLK/SCL
SDIO/SDA
SDO
CS
SPI
I²C
INTERFACE INTERFACE
DIVIDE BY
1 TO 32
CPRSET VCP
LOCK
DETECT
HOLD
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE BY
1 TO 32
AD9522
DIVIDE BY
1 TO 32
Figure 37. Internal VCO and Clock Distribution (Mode 0)
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
OUT10
OUT10
OUT11
OUT11
Rev. 0 | Page 28 of 84