AD9684 Datasheet, PDF (7/64 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

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AD9684
Parameter
DIGITAL OUTPUTS (Dx±,¹ DCO±, STATUS±)
Logic Compliance
Differential Output Voltage
Output Common-Mode Voltage (VCM)
AC-Coupled
Short-Circuit Current (IDSHORT)
Differential Return Loss (RLDIFF)²
Common-Mode Return Loss (RLCM) ²
Differential Termination Impedance
Temperature
Full
Full
25°C
25°C
25°C
25°C
Full
1 _{Where x = 0 to 13.}
2 _{Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.}
Min
230
0
−100
8
6
80
Typ
LVDS
100
Max
Unit
430
1.8
+100
120
mV p-p
V
mA
dB
dB
Ω
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise
noted.
Table 4.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Maximum Sample Rate¹
Minimum Sample Rate²
Clock Pulse Width
High
Low
LVDS DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)³
DCO± Propagation Delay (tDCO)³
DCO± to Data Skew
Rising Edge Data (tSKEWR)³
Falling Edge Data (tSKEWF)³
STATUS± Propagation Delay (tSTATUS)⁴
DCO± to STATUS± Skew (tFRAME)⁴
Data Propagation Delay (tPD)³
DCO± Propagation Delay (tDCO)³
LATENCY⁵
Pipeline Latency
Fast Detect Latency
HB1 Filter Latency³
HB1 + HB2 Filter Latency³
HB1 + HB2 + HB3 Filter Latency³
HB1 + HB2 + HB3 + HB4 Filter Latency³
Fast Detect Latency
Wake-Up Time⁶
Standby
Power-Down
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Min
0.25
500
250
1000
1000
−150
850
−150
Typ Max
4
2.225
2.2
−25
1.025
2.2
−25
2.225
2.2
+100
1100
+100
35
28
50
101
217
433
28
1
4
Unit
GHz
MSPS
MSPS
ps
ps
ns
ns
ps
ps
ns
ps
ns
ns
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ms
ms
Rev. 0 | Page 7 of 64