AD9684 Datasheet, PDF (11/64 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

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AD9684
VIN±x
APERTURE DELAY
N
N+x
N + 36
N + 37
N + 38
SYNC+
SYNC–
CLK+
CLK–
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
CONSTANT LATENCY = X CLK CYCLES
t_DCO
t_PD
t_CLK
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
STATUS BIT SELECTED BY
REGISTER 0x559, BITS[2:0]
IN THE REGISTER MAP
STATUS+
(OVERRANGE/STAUS BIT)
STATUS–
STATUS STATUS
t_SKEWR
t_SKEWF
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 2]
STATUS STATUS STATUS STATUS STATUS STATUS
CHANNEL A D12±/D13±
CHANNEL A D0±/D1±
S[N – y]
S[N – x]
(ODD BITS) (EVEN BITS)
S[N – 1]
S[N]
S[N]
S[N + 1]
S[N + 1]
S[N + 2]
(ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)
Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data
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