AD9684 Datasheet, PDF (51/64 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

Product
Overview
Data Sheet
Online
Documentation
Design
Resources
Discussion
Sample
& Buy
AD9684
TEST MODES
ADC TEST MODES
The AD9684 has various test options that aid in the system level
implementation. The AD9684 has ADC test modes that are
available in Register 0x550. These test modes are described in
Table 26. When an output test mode is enabled, the analog
section of the ADC is disconnected from the digital back-end
blocks and the test pattern is run through the output formatting
block. Some of the test patterns are subject to output formatting,
and some are not. The pseudorandom number (PN) generators
from the PN sequence tests can be reset by setting Bit 4 or Bit 5
of Register 0x550. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored);
however, they do require an encode clock. For more information,
see the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
Table 26. ADC Test Modes
Output Test Mode
Bit Sequence
Pattern Name
0000
Off (default)
0001
Midscale short
0010
+Full-scale short
0011
−Full-scale short
0100
Checkerboard
0101
PN sequence
long
0110
PN sequence
short
0111
One-/zero-word
toggle
1000
User input
Expression
Not applicable
00 0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
x²³ + x¹⁸ + 1
x⁹ + x⁵ + 1
11 1111 1111 1111
Register 0x551 to
Register 0x558
1111
Ramp output
(x) % 2¹⁴
Default/Seed
Value
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
0x3AFF
0x0092
Not applicable
Not applicable
Not applicable
Sample (N, N + 1, N + 2, …)
Not applicable
Not applicable
Not applicable
Not applicable
0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]…
For single mode: User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2], 0x0000…
(x) % 2¹⁴, (x + 1) % 2¹⁴, (x + 2) % 2¹⁴, (x + 3) % 2¹⁴
Rev. 0 | Page 51 of 64