AD9684 Datasheet, PDF (48/64 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

AD9684
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MULTICHIP SYNCHRONIZATION
The AD9684 has a SYNC± input that allows the user flexible
options for synchronizing the internal blocks. The SYNC±
input is a source synchronous system reference signal that
enables multichip synchronization. The input clock divider,
DDCs, and signal monitor block LVDS output link can be
synchronized using the SYNC± input. For the highest level of
timing accuracy, SYNC± must meet the setup and hold
requirements relative to the CLK± input.
The flowchart in Figure 67 shows the internal mechanism by
which multichip synchronization can be achieved in the AD9684.
START
The AD9684 supports several features that aid users in meeting
the requirements for capturing SYNC± signals. The SYNC±
sample event can be defined as either a synchronous low to high
transition or a synchronous high to low transition. Additionally,
the AD9684 allows the SYNC± signal to be sampled using
either the rising edge or the falling edge of the CLK± input. The
AD9684 can also to ignore a programmable number (up to 16)
of SYNC± events. The SYNC± control options can be selected
using Register 0x120 and Register 0x121.
INCREMENT
SYNC± IGNORE
COUNTER
NO
RESET
SYNC± IGNORE
COUNTER
NO
SYNC±
ENABLED?
YES
REG (0x120)
NO
SYNC±
ASSERTED?
YES
UPDATE
SETUP/HOLD
DETECTOR STATUS
REG (0x128)
NO
SYNC±
IGNORE
COUNTER
EXPIRED?
REG (0x121)
YES
ALIGN CLOCK
DIVIDER
PHASE TO
SYNC±
YES
INPUT
CLOCK
DIVIDER
ALIGNMENT
REQUIRED?
NO
YES
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
REG (0x10D)
YES
CLOCK
DIVIDER
> 1?
REG (0x10B)
NO
NO
INCREMENT
SYNC±
COUNTER
REG (0x12A)
CLOCK
ALIGNMENT
REQUIRED?
YES
ALIGN PHASE OF ALL
INTERNAL CLOCKS
TO SYNC±
NO
SIGNAL
MONITOR
SYNC
ENABLED?
REG (0x26F)
NO
YES
ALIGN SIGNAL
MONITOR
COUNTERS
DDC NCO
ALIGNMENT
ENABLED?
REG (0x300)
YES
ALIGN DDC
NCO PHASE
ACCUMULATOR
NO
Figure 67. Multichip Synchronization
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