AD4000_17 Datasheet, PDF (7/36 Pages) Analog Devices – Precision, Pseudo Differential, SAR ADCs

Data Sheet
AD4000/AD4004/AD4008
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled,
turbo mode enabled, and fS = 2 MSPS for the AD4000, fS = 1 MSPS for the AD4004, and fS = 500 kSPS for the AD4008, unless otherwise noted.
See Figure 2 for the timing voltage levels.
Table 2. Digital Interface Timing
Parameter
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE
ACQUISITION PHASE¹
AD4000
AD4004
AD4008
TIME BETWEEN CONVERSIONS
AD4000
AD4004
AD4008
CNV PULSE WIDTH (CS MODE)²
SCK PERIOD (CS MODE)³
VIO > 2.7 V
VIO > 1.7 V
SCK PERIOD (DAISY-CHAIN MODE)⁴
VIO > 2.7 V
VIO > 1.7 V
SCK LOW TIME
SCK HIGH TIME
SCK FALLING EDGE TO DATA REMAINS VALID DELAY
SCK FALLING EDGE TO DATA VALID DELAY
VIO > 2.7 V
VIO > 1.7 V
CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE)
VIO > 2.7 V
VIO > 1.7 V
CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY
LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY⁵
CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)
SDI VALID SETUP TIME FROM CNV RISING EDGE
SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE)
SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)
SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tQUIET1
tQUIET2
tDIS
tSSDICNV
tHSDICNV
tHSCKCNV
tSSDISCK
tHSDISCK
Min Typ Max Unit
270 290 320 ns
290
ns
790
ns
1790
ns
500
ns
1000
ns
2000
ns
10
ns
9.8
ns
12.3
ns
20
ns
25
ns
3
ns
3
ns
1.5
ns
7.5 ns
10.5 ns
10
ns
13
ns
190
ns
60
ns
20
ns
2
ns
2
ns
12
ns
2
ns
2
ns
1 _{The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the}
AD4000, 1 MSPS for the AD4004, and 500 kSPS for the AD4008.
2 _{For turbo mode, tCNVH must match the tQUIET1 minimum.}
3 _{A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable}
throughput for different modes of operation.
4 _{A 50% duty cycle is assumed for SCK.}
5 _{See Figure 22 for SINAD, SNR, and ENOB vs. tQUIET2.}
X% VIO¹
Y% VIO¹
t_DELAY
t_DELAY
V_IH2
V_IL2
V_IH2
V_IL2
1_{FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.}
2_{MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS}
SPECIFICATIONS IN TABLE 1.
Figure 2. Voltage Levels for Timing
Rev. C | Page 7 of 36