AD4000_17 Datasheet, PDF (23/36 Pages) Analog Devices – Precision, Pseudo Differential, SAR ADCs

Data Sheet
Figure 42 and Figure 43 show the AD4000/AD4004/AD4008
SNR and THD performance using the ADA4077-1 (supply
current per amplifier (ISY) = 400 µA) and ADA4610-1 (ISY =
1.50 mA) precision amplifiers when driving the AD4000/AD4004/
AD4008 at full throughput for high-Z mode both enabled and
disabled with various RC filter values. These amplifiers achieve
91 dB to 92 dB typical SNR and close to −100 dB typical THD
with high-Z enabled for a 2.27 MHz RC bandwidth. THD is
approximately 5 dB better with high-Z mode enabled, even for
large R values greater than 200 Ω. SNR maintains close to 85 dB
even with a very low RC filter cutoff.
When high-Z mode is enabled, the ADC consumes approximately
1 mW per MSPS of extra power; however, this is still significantly
lower than using dedicated ADC drivers like the ADA4807-1.
For any system, the front end usually limits the overall ac/dc
performance of the signal chain. The data sheets of the selected
precision amplifiers, shown in Figure 42 and Figure 43, show
that their own noise and distortion performance dominates the
SNR and THD specification at a certain input frequency.
95
90
85
80
75
ADA4077-1 HIGH-Z ENABLED
ADA4077-1 HIGH-Z DISABLED
ADA4610-1 HIGH-Z ENABLED
ADA4610-1 HIGH-Z DISABLED
70
260.482kHz 497.981kHz
1.3kΩ
680Ω
470pF
470pF
1.3MHz
680Ω
180pF
2.27MHz
390Ω
180pF
RC FILTER BANDWIDTHS (Hz),
RESISTOR (Ω), CAPACITOR (pF)
4.42MHz
200Ω
180pF
Figure 42. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled),
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
AD4000/AD4004/AD4008
–70
–75
–80
–85
–90
–95
–100
–105
ADA4077-1 HIGH-Z ENABLED
–110
ADA4077-1 HIGH-Z DISABLED
ADA4610-1 HIGH-Z ENABLED
ADA4610-1 HIGH-Z DISABLED
–115
260.482kHz 497.981kHz 1.3MHz
2.27MHz
1.3kΩ
680Ω
680Ω
390Ω
470pF
470pF
180pF
180pF
RC FILTER BANDWIDTHS (Hz),
RESISTOR (Ω), CAPACITOR (pF)
4.42MHz
200Ω
180pF
Figure 43. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers,
fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled),
VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C
Long Acquisition Phase
The AD4000/AD4004/AD4008 also feature a fast conversion
time of 290 ns, which results in a long acquisition phase. The
acquisition is further extended by a key feature of the AD4000/
AD4004/AD4008: the ADC returns to the acquisition phase
typically 100 ns before the end of the conversion. This feature
provides an even longer time for the ADC to acquire the new
input voltage. A longer acquisition phase reduces the settling
requirement on the driving amplifier, and a lower power/
bandwidth amplifier can be chosen. The longer acquisition
phase means that a lower RC filter (represented by R and C in
Figure 33 and Figure 34) cutoff can be used, which means a
noisier amplifier can also be tolerated. A larger value of R can
be used in the RC filter with a corresponding smaller value of C,
reducing amplifier stability concerns without affecting distortion
performance significantly. A larger value of R also results in
reduced dynamic power dissipation in the amplifier.
See Table 10 for details on setting the RC filter bandwidth and
choosing a suitable amplifier.
VOLTAGE REFERENCE INPUT
A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate
for the optimum performance of the reference input.
For higher performance and lower drift, use a reference such as
the ADR4550. Use a low power reference such as the ADR3450
at the expense of a slight decrease in the noise performance. It is
recommended to use a reference buffer such as the ADA4807-1
between the reference and the ADC reference input. It is important
to consider the optimum capacitance necessary to keep the
reference buffer stable as well as to meet the minimum ADC
requirement stated previously in this section (that is, a 10 µF
ceramic chip capacitor, CREF).
Rev. C | Page 23 of 36