AD4000_17 Datasheet, PDF (29/36 Pages) Analog Devices – Precision, Pseudo Differential, SAR ADCs

Data Sheet
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host.
The connection diagram is shown in Figure 52, and the
corresponding timing diagram is shown in Figure 53.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion is initiated, it continues until
completion irrespective of the state of CNV. This feature can be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
AD4000/AD4004/AD4008
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
When the conversion is complete, the AD4000/AD4004/AD4008
enter the acquisition phase and power down. When CNV goes
low, the MSB is output onto SDO. The remaining data bits are
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16^th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
There must not be any digital activity on SCK during the
conversion.
SDI = 1
CNV
t_CNVH
ACQUISITION
SCK
SDO
VIO
SDI
CNV
AD4000/
AD4004/ SDO
AD4008
SCK
CONVERT
DIGITAL HOST
DATA IN
CLK
Figure 52. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
t_CYC
CONVERSION
t_CONV
t_ACQ
ACQUISITION
t_SCKL
t_SCK
t_QUIET2
1
2
3
14
15
16
t_HSDO
t_SCKH
t_EN
t_DSDO
t_DIS
D15
D14
D13
D1
D0
Figure 53. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)
Rev. C | Page 29 of 36