AD4000_17 Datasheet, PDF (1/36 Pages) Analog Devices – Precision, Pseudo Differential, SAR ADCs

Data Sheet
16-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Pseudo Differential, SAR ADCs
AD4000/AD4004/AD4008
FEATURES
and AD4008 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
Throughput: 2 MSPS/1 MSPS/500 kSPS options
respectively. They incorporate ease of use features that reduce
INL: ±1.0 LSB maximum
signal chain power consumption, reduce signal chain complexity,
Guaranteed 16-bit, no missing codes
and enable higher channel density. The high-Z mode, coupled
Low power
with a long acquisition phase, eliminates the need for a dedicated
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
high power, high speed ADC driver, thus broadening the range
(VDD only)
of low power precision amplifiers that can drive these ADCs
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
directly while still achieving optimum performance. The input
SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz
span compression feature enables the ADC driver amplifier and
THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz
the ADC to operate off of common supply rails without the need
Ease of use features reduce system power and complexity
for a negative supply while preserving the full ADC code range.
Input overvoltage clamp circuit
The low serial peripheral interface (SPI) clock rate requirement
Reduced nonlinear input charge kickback
reduces the digital input/output power consumption, broadens
High-Z mode
processor options, and simplifies the task of sending data across
Long acquisition phase
digital isolation.
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first conversion
First conversion accurate
Guaranteed operation: −40°C to +125°C
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
Operating from a 1.8 V supply, the AD4000/AD4004/AD4008
sample an analog input (IN+) from 0 V to VREF with respect to
a ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V.
The AD4000 consumes only 14 mW at 2 MSPS with a minimum
SCK rate of 70 MHz in turbo mode, the AD4004 consumes only
7 mW at 1 MSPS, and the AD4008 consumes only 3.5 mW at
500 kSPS. The AD4000/AD4004/AD4008 all achieve ±1.0 LSB
integral nonlinearity error (INL) maximum, guaranteed no
missing codes at 16 bits, and 93 dB signal-to-noise ratio (SNR)
for 1 kHz inputs. The reference voltage is applied externally and
can be set independently of the supply voltage.
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
The SPI-compatible versatile serial interface features seven
different modes including the ability, using the SDI input, to
daisy-chain several ADCs on a single 3-wire bus, and provides
an optional busy indicator. The AD4000/AD4004/AD4008 are
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the
separate VIO supply.
GENERAL DESCRIPTION
The AD4000/AD4004/AD4008 are low noise, low power, high
speed, 16-bit, precision successive approximation register (SAR)
analog-to-digital converters (ADCs). The AD4000, AD4004,
The AD4000/AD4004 are available in a 10-lead MSOP and a
10-lead LFCSP, and the AD4008 is available in a 10-lead LFCSP,
with operation specified from −40°C to +125°C. The devices are
pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8).
FUNCTIONAL BLOCK DIAGRAM
2.4V TO 5.1V 1.8V
10µF REF
VDD
V_REF
V_REF/2
0
AD4000/
HIGH-Z AD4004/
IN+
MODE _AD4008
16-BIT
SAR ADC
IN–
CLAMP
SPAN
COMPRESSION
TURBO
MODE
SERIAL
INTERFACE
STATUS
BITS
GND
VIO _{1.8V TO 5V}
SDI
SCK
SDO
CNV
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
Figure 1.
Rev. C
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