AD9516-5BCPZ Datasheet, PDF (69/76 Pages) Analog Devices – 14-Output Clock Generator

AD9516-5
Reg.
Addr.
(Hex) Bits Name
2
Divider 4 force high
1
Start High Divider 4.2
0
Start High Divider 4.1
0x1A2 0
Divider 4 DCCOFF
Description
Forces Divider 4 output high. Requires that the Divider 4 nosync bit (Bit 3) also be set.
0: forces low (default).
1: forces high.
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 55. VCO Divider and CLK Input
Reg.
Addr.
(Hex) Bits
Name
0x1E0 [2:0] VCO divider
0x1E1 4
0
Power-down clock input
section
Bypass VCO divider
Description
2 1 0 Divide
0 002
0 013
0 1 0 4 (default)
0 115
1 006
1 0 1 Output static
1 1 0 Output static
1 1 1 Output static
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: powers down.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider.
Table 56. System
Reg.
Addr.
(Hex) Bits
Name
230 2
Power-down SYNC
1
Power-down distribution
reference
0
Soft SYNC
Description
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down the SYNC circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is
reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-
to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Rev. A | Page 69 of 76