AD9516-5BCPZ Datasheet, PDF (41/76 Pages) Analog Devices – 14-Output Clock Generator

AD9516-5
The most common way to execute the SYNC function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The timing
of the SYNC operation is shown in Figure 45 (using VCO divider)
and Figure 46 (VCO divider not used). There is an uncertainty
of up to one cycle of the clock at the input to the channel divider
due to the asynchronous nature of the SYNC signal with respect
to the clock edges inside the AD9516. The delay from the SYNC
rising edge to the beginning of synchronized output clocking is
between 14 and 15 cycles of clock at the channel divider input,
plus either one cycle of the VCO divider input (see Figure 45),
or one cycle of the CLK input (see Figure 46), depending on
whether the VCO divider is used. Cycles are counted from the
rising edge of the signal.
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0] (see Table 47
through Table 57 for details). Both the setting and resetting of
the soft SYNC bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
1
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
Figure 45. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER
OUTPUT CLOCKING
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 46. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
Rev. A | Page 41 of 76