AD9516-5BCPZ Datasheet, PDF (17/76 Pages) Analog Devices – 14-Output Clock Generator

AD9516-5
Pin No.
16
17
21
22
23
24
25
26
27, 41, 54
28
29
33
34
35
36
37, 44, 59,
EPAD
39
40
42
43
45
46
47
48
52
53
55
56
58
62
63
64
Input/
Output
I
I
O
I/O
I
I
O
O
I
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
Pin Type
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
LVPECL
LVPECL
Power
LVPECL
LVPECL
LVDS or CMOS
LVDS or CMOS
LVDS or CMOS
LVDS or CMOS
GND
LVPECL
LVPECL
LVPECL
LVPECL
LVDS or CMOS
LVDS or CMOS
LVDS or CMOS
LVDS or CMOS
LVPECL
LVPECL
LVPECL
LVPECL
Current set
resistor
Current set
resistor
Reference
input
Reference
input
Mnemonic
SCLK
CS
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
GND
OUT3
OUT3
OUT2
OUT2
OUT7 (OUT7B)
OUT7 (OUT7A)
OUT6 (OUT6B)
OUT6 (OUT6A)
OUT1
OUT1
OUT0
OUT0
RSET
Description
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port Unidirectional Serial Data Output.
Serial Control Port Bidirectional Serial Data Input/Output.
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
Ground Pins, Including External Paddle (EPAD). The external die paddle on the
bottom of the package must be connected to ground for proper operation.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.
CPRSET
REFIN (REF2)
REFIN (REF1)
A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.
This resistor can be omitted if the PLL is not used.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2. This pin can be left
unconnected when the PLL is not used.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1. This pin can be left
unconnected when the PLL is not used.
Rev. A | Page 17 of 76