AD9516-5BCPZ Datasheet, PDF (25/76 Pages) Analog Devices – 14-Output Clock Generator

AD9516-5
THEORY OF OPERATION
REF_SEL
VS GND
RSET
REFMON
CPRSET VCP
REFIN (REF1)
REFIN (REF2)
REF1
REF2
REFERENCE
SWITCHOVER
STATUS
STATUS
DISTRIBUTION
REFERENCE
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
LOCK
DETECT
LD
HOLD
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
DIVIDE BY
2, 3, 4, 5, OR 6
10
SERIAL
CONTROL
PORT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-5
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
STATUS
LVPECL
LVPECL
LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6 (OUT6A)
∆t
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
OUT8 (OUT8B)
LVDS/CMOS
OUT9 (OUT9A)
∆t
OUT9 (OUT9B)
Figure 33. Clock Distribution or External VCO < 1600 MHz (Mode 1)
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 47 and Table 48 through Table 57). Each section or
function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
Mode 1—Clock Distribution or External VCO < 1600 MHz
For clock distribution applications where the external clock is less
than 1600 MHz, use the register settings shown in Table 18.
Table 18. Settings for Clock Distribution < 1600 MHz
Register
Description
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
Mode 1 bypasses the VCO divider. Mode 1 can be used only
When using the internal PLL with an external VCO of <1600 MHz,
with an external clock source of <1600 MHz, due to the maximum
the PLL must be turned on.
input frequency allowed at the channel dividers.
Rev. A | Page 25 of 76