AD9516-1 Datasheet, PDF (64/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

AD9516-1
Reg.
Addr
(Hex) Bit(s) Name
Description
19 <7:6> R, A, B
<7> <6> Action
Counters 0
0
Do nothing on SYNC (default).
SYNC Pin 0
1
Asynchronous reset.
Reset
1
0
Synchronous reset.
1
1
Do nothing on SYNC.
19 <5:3> R Path Delay <5:3> R Path Delay (see Table 2).
19 <2:0> N Path Delay <2:0> N Path Delay (see Table 2).
1A <6> Reference Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect
Frequency the VCO frequency monitor’s detection threshold (see Table 16, REF1, REF2, and VCO Frequency Status Monitor).
Monitor <6> = 0; frequency valid if frequency is above the higher frequency threshold
Threshold <6> = 1; frequency valid if frequency is above the lower frequency threshold
1A <5:0> LD Pin
Select the signal which is connected to the LD pin.
Control
<5> <4> <3> <2>
Level or
Dynamic
<1> <0> Signal Signal at LD Pin
0 00 0
0 0 LVL
Digital lock detect (high = lock, low = unlock).
0 00 0
0 1 DYN P-channel, open-drain lock detect (analog lock detect).
0 00 0
1 0 DYN N-channel, open-drain lock detect (analog lock detect).
0 00 0
1 1 HIZ
High-Z LD pin.
0 00 1
0 0 CUR Current source lock detect (110 μA when DLD is true).
0 XX X
X X LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1 00 0
0 0 LVL
Ground (dc).
1 00 0
0 1 DYN REF1 clock (differential reference when in differential mode).
1 00 0
1 0 DYN REF2 clock (N/A in differential mode).
1 00 0
1 1 DYN
Selected reference to PLL (differential reference when in
differential mode).
1 00 1
0 0 DYN Unselected reference to PLL (not available in differential mode).
1 00 1
0 1 LVL
Status of selected reference (status of differential reference);
active high.
1 00 1
1 0 LVL
Status of unselected reference (not available in differential
mode); active high.
1 00 1
1 1 LVL
Status REF1 frequency (active high).
1 01 0
0 0 LVL
Status REF2 frequency (active high).
1 01 0
0 1 LVL
(Status REF1 frequency) AND (status REF2 frequency).
1 01 0
1 0 LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1 01 0
1 1 LVL
Status of VCO frequency (active high).
1 01 1
0 0 LVL
Selected reference (Low = REF1, High = REF2).
1 01 1
0 1 LVL
Digital lock detect (DLD); active high.
1 01 1
1 0 LVL
Holdover active (active high).
1 01 1
1 1 LVL
N/A—do not use.
1 10 0
0 0 LVL
VS (PLL supply).
1 10 0
0 1 DYN REF1 clock _{(differential reference when in differential mode).}
1 10 0
1 0 DYN REF2 clock _{(not available in differential mode).}
1 10 0
1 1 DYN
Selected reference to PLL (differential reference when in
differential mode).
1 10 1
0 0 DYN
Unselected reference to PLL (not available when in differential
mode).
1 10 1
0 1 LVL
Status of selected reference (status of differential reference);
active low.
Rev. 0 | Page 64 of 84