AD9516-1 Datasheet, PDF (45/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (DX.1 × DX.2) can be realized.
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)); however,
with these channel dividers, the number of possible
configurations is even more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
• An even DX.Y must be set with the MX.Y = NX.Y (low cycles =
high cycles).
• An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of
low cycles must be one greater than the number of high cycles).
• If only one divider is bypassed, it must be the second
divider, X.2.
• If only one divider has an even divide by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 40 through Table 44.
Table 40. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
DX.1
NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output Duty Cycle
Even
1
1
50%
Odd = 3 1
1
33.3%
Odd = 5 1
1
40%
Even
Even, Odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Odd
Even, Odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Even
Even, Odd
Even, Odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Odd
Even, Odd
Even, Odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
AD9516-1
Table 41. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
DX.1
DX.2
Output
Duty Cycle _{NX.1 + MX.1 + 2 NX.2 + MX.2 + 2} Duty Cycle
50%
1
1
50%
X%
1
1
X%
50%
Even, Odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
X%
Even, Odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
50%
Even, Odd
Even, Odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
X%
Even, Odd
Even, Odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 42. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
DX.1
NX.1 + MX.1 + 2
1
1
Even (NX.1 = MX.1)
Even (NX.1 = MX.1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Even (NX.1 = MX.1)
Even (NX.1 = MX.1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
DX.2
NX.2 + MX.2 + 2
1
1
1
1
1
1
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Odd (MX.2 = NX.2 + 1)
Odd (MX.2 = NX.2 + 1)
Output
Duty Cycle
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
Rev. 0 | Page 45 of 84