AD9516-1 Datasheet, PDF (15/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

TIMING DIAGRAMS
CLK
t_CLK
t_PECL
t_LVDS
t_CMOS
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL
80%
20%
LVPECL
t_RP
t_FP
Figure 3. LVPECL Timing, Differential
AD9516-1
DIFFERENTIAL
80%
20%
LVDS
t_RL
t_FL
Figure 4. LVDS Timing, Differential
SINGLE-ENDED
80%
20%
CMOS
10pF LOAD
t_RC
t_FC
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
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