AD9516-1 Datasheet, PDF (60/84 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

AD9516-1
REGISTER MAP DESCRIPTIONS
Table 52 through Table 61 are a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. Example: <3> refers to Bit 3, while
<5:2> refers to the range of bits from Bit 5 through Bit 2.
Table 52. Serial Port Configuration
Reg. Addr (Hex) Bit(s) Name
00
<7> SDO Active
00
<6> LSB First
00
<5> Soft Reset
00
<4> Long Instruction
00
<3:0> Mirror<7:4>
04
<0> Read Back Active Registers
Description
Selects unidirectional or bidirectional data transfer mode.
<7> = 0; SDIO pin used for write and read; SDO set high impedance; bidirectional mode.
<7> = 1; SDO used for read; SDIO used for write; unidirectional mode.
MSB or LSB data orientation.
<6> = 0; data-oriented MSB first; addressing decrements.
<6> = 1; data-oriented LSB first; addressing increments.
Soft Reset.
<5> = 1 (not self-clearing). Soft reset; restores default values to internal registers.
Not self-clearing. Must be cleared to 0b to complete reset operation.
Short/long instruction mode (this part uses long instruction mode only, so this bit
should always be = 1).
<4> = 0; 8-bit instruction (short).
<4> = 1; 16-bit instruction (long).
Bits<3:0> should always mirror<7:4> so that it does not matter whether the part
is in MSB or LSB first mode (see Register 0x00<6>). User should set bits as follows:
<0> = <7>
<1> = <6>
<2> = <5>
<3> = <4>
Select register bank used for a readback.
<0> = 0; read back buffer registers.
<0> = 1; read back active registers.
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