ADSP-21469BBCZ-3 Datasheet, PDF (60/72 Pages) Analog Devices – SHARC Processor

ADSP-21469
4
3.5
TYPE C & D HALF DRIVE FALL
3
y = 0.0841x + 0.8997
TYPE C & D HALF DRIVE RISE
y = 0.0617x + 0.7995
2.5
TYPE C & D FULL
DRIVE FALL
y = 0.0421x + 0.9257
2
1.5
TYPE C & D FULL
DRIVE RISE
1
y = 0.0304x + 0.8204
0.5
00
5
10
15
20
25
30
35
40
LOAD CAPACITANCE (pF)
Figure 51. Typical Output Rise/Fall Time DDR2
(20% to 80%, V_{DD_EXT} = Min)
10
9
8
7
6
5
4
3
2
1
0
0
TYPE A DRIVE FALL
y = 0.0359x + 2.9227
TYPE A DRIVE RISE
y = 0.0256x + 3.5876
TYPE B DRIVE RISE
y = 0.0116x + 3.5697
TYPE B DRIVE FALL
y = 0.0136x + 3.1135
25
50
75
100 125 150 175 200
LOAD CAPACITANCE (pF)
Figure 52. Typical Output Rise/Fall Delay Non-DDR
(V_{DD_EXT} = Min)
4.5
TYPE A FALL
4
y = 0.0196x + 1.2934
TYPE A RISE
y = 0.0152x + 1.7611
3.5
TYPE B RISE
y = 0.0060x + 1.7614
3
2.5
TYPE B FALL
2
y = 0.0074x + 1.421
1.5
1
0.5
0
0
25
50
75
100
125 150 175 200
LOAD CAPACITANCE (pF)
Figure 53. Typical Output Rise/Fall Delay No- DDR
(V_{DD_EXT} = Max)
3.0
2.8
TYPE C HALF DRIVE (FALL)
y = 0.0122x + 2.0405
2.6
TYPE C HALF DRIVE (RISE)
y = 0.0079x + 2.0476
2.4
2.2
2.0
1.8
1.6
1.4
0
TYPE C FULL DRIVE (RISE & FALL)
y = 0.0023x + 1.9472
5
10
15
20
25
30
35
LOAD CAPACITANCE (pF)
Figure 54. Typical Output Rise/Fall Delay DDR Pad C
(V_{DD_EXT} = Min)
Rev. 0 | Page 60 of 72 | June 2010