ADSP-21469BBCZ-3 Datasheet, PDF (50/72 Pages) Analog Devices – SHARC Processor

ADSP-21469
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 47. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 47. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
t_SISFS¹
Frame Sync Setup Before Serial Clock Rising Edge
3
ns
t_SIHFS¹
Frame Sync Hold After Serial Clock Rising Edge
3
ns
t_SISD¹
Data Setup Before Serial Clock Rising Edge
3
ns
t_SIHD¹
Data Hold After Serial Clock Rising Edge
3
ns
t_SITXCLKW
Transmit Clock Width
9
ns
t_SITXCLK
Transmit Clock Period
20
ns
t_SISCLKW
Clock Width
36
ns
t_SISCLK
Clock Period
80
ns
1 _{The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can}
be either CLKIN or any of the DAI pins.
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t_SITXCLKW
SAMPLE EDGE
t_SITXCLK
t_SISCLKW
t_SISCLK
t_SISFS
t_SISD
t_SIHFS
t_SIHD
Figure 36. S/PDIF Transmitter Input Timing
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 48. Oversampling Clock (HFCLK) Switching Characteristics
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (Fs)
Max
Oversampling Ratio × Frame Sync <= 1/t_SIHFCLK
49.2
192.0
Unit
MHz
MHz
kHz
Rev. 0 | Page 50 of 72 | June 2010