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| ADSP-21469BBCZ-3 Datasheet, PDF (49/72 Pages) Analog Devices – SHARC Processor | |||
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Table 46. S/PDIF Transmitter Left-Justified Mode
Parameter
Timing Requirement
tLJD
LRCLK to MSB Delay in Left-Justified Mode
Nominal
0
DAI_P20â1
LRCLK
DAI_P20â1
SCLK
DAI_P20â1
SDATA
LEFT/RIGHT CHANNEL
tLJD
MSB MSBâ1 MSBâ2
LSB+2 LSB+1 LSB
Figure 35. Left-Justified Mode
ADSP-21469
Unit
SCLK
Rev. 0 | Page 49 of 72 | June 2010
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