ADSP-21469BBCZ-3 Datasheet, PDF (1/72 Pages) Analog Devices – SHARC Processor

SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM
Up to 450 MHz operating frequency
Qualified for automotive applications, see Automotive Prod-
ucts on Page 70
Code compatible with all other members of the SHARC family
SHARC Processor
ADSP-21469
The ADSP-21469 processor is available with unique audio-
centric peripherals such as the digital applications
interface, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more.
For complete ordering information, see Ordering Guide on
Page 70
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
PEx
Timer
PEy
FLAGx/IRQx/
TMREXP
JTAG
THERMAL
DIODE
DMD
64-BIT
PMD
64-BIT
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
SPI/B UART
DPI Routing/Pins
DPI Peripherals
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
Core Bus
Cross Bar
DMD
64-BIT
PMD 64-BIT
EPD BUS 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
PERIPHERAL
BUS 32-BIT
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC ^PDAP/ SPORT
3-0 ^IDP 7-0
7-0
DAI Routing/Pins
DAI Peripherals
IOD1
32-BIT
FFT _DTCP/
FIR _MTM
IIR
SPEP BUS
LINK _{CORE PWM}
MLB PORT _{FLAGS 3-0}
1-0
EP
AMI ^DDR2
CTL
External Port Pin MUX
External
Port
Peripherals
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. 0
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