EVAL-AD1955EB Datasheet, PDF (6/24 Pages) Analog Devices – High Performance Multibit
- DAC with SACD Playback

AD1955
Pin No.
1
2
I/O
Input
3
Input
4
Input
5
Input
6
I/O
7
Input
8
Input
9
I/O
10
11
Output
12
Output
13
Output
14
15
16
Output
17
Output
18
Output
19
20
Output
21
Output
22
Input
23
Input
24
Input
25
Input
26
Input
27
Input
28
PIN FUNCTION DESCRIPTIONS
Mnemonic
DVDD
LRCLK/EF_WCLK
BCLK/EF_BCLK
SDATA/EF_LDATA
EF_RDATA
DSD_SCLK
DSD_LDATA
DSD_RDATA
DSD_PHASE
AGND
IOUTR+
IOUTR–
FILTR
IREF
AVDD
FILTB
IOUTL–
IOUTL+
AGND
ZEROR
ZEROL
MUTE
PD/RST
CDATA
CLATCH
CCLK
MCLK
DGND
Description
Digital Power Supply Connected to Digital 5 V Supply
Left/Right Clock Input for Input Data in PCM Mode
Word Clock in External Filter Mode
Bit Clock Input for Input Data in PCM Mode
Bit Clock Input in External Filter Mode
MSB First, Twos Complement Serial Audio Data
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
Not used in PCM Mode
Right channel data in External Filter Mode
Serial Clock Input for DSD Data. This clock should be 64 Ï« 44.1 kHz,
2.8224 MHz or 128 Ï« 44.1 kHz, 5.6448 MHz in Normal Mode, 128 Ï«
44.1 kHz, 5.6448 MHz or 256 Ï« 44.1 kHz, 11.2896 MHz in Phase Mode.
DSD Left Channel Data Input
DSD Right Channel Data Input
DSD Phase Reference Signal. This clock should be 64 Ï« 44.1 kHz,
2.8224 MHz. If not used, this pin should be connected low.
Analog Ground
Right Channel Positive Analog Output
Right Channel Negative Analog Output
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.
Connection Point for External Bias Resistor
Analog Power Supply Connected to Analog 5 V Supply
Filter Capacitor Connection with Parallel 10 µF and 0.1 µF Capacitors to AGND
Left Channel Negative Analog Output
Left Channel Positive Analog Output
Analog Ground
Right Channel Zero Flag Output. This pin goes high when the right channel
has no signal input or the DSD mute pattern is detected.
Left Channel Zero Flag Output. This pin goes high when the left channel has
no signal input or the DSD mute pattern is detected.
Mute. Assert high to mute both stereo analog outputs. Deassert low for nor-
mal operation.
Power Down/Reset. The AD1955 is placed in a reset state and the digital
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used
for specifying control information and channel-specific attenuation.
Latch Input for Control Data
Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
Master Clock Input. Connect to an external clock source.
Digital Ground
–6–
REV. 0