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EVAL-AD1955EB Datasheet, PDF (14/24 Pages) Analog Devices – High Performance Multibit - DAC with SACD Playback
AD1955
For example, with the stereo circuits given in Figures 7 through
10, this gives:
[ ] [ ] 12.0V – 2.80V 3.24 mA + (2.80V 2.00 K ) = 1.98 kΩ
A 2.00 kΩ resistor is used.
The supply used should be as quiet as possible.
Serial Control Port
The AD1955 has an SPI compatible control port to permit pro-
gramming the internal control registers. The SPI control port is
a 3-wire serial port. Its format is similar to the Motorola SPI
format except that the input data-word is 16 bits wide. The serial
bit clock may be completely asynchronous to the sample rate of the
DAC. The following figure shows the format of the SPI signal
Note that the CCLK may be continuous or a 16-clock burst.
SPI REGISTER DEFINITIONS
Table I. DAC Control Register 0
Bit Description
15
Power-Down
14
Mute
13:12 Data Format
11:10 Output Format
9:8 PCM Sample Rate
7:6 De-Emphasis Curve
Select
5:4 PCM/EF Serial Data
Format
3:2 PCM/EF Serial Data
Width
1:0 SPI Register Address
Default = 0
Value
0
1
0
1
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
Definition
Operation
Powered Down
Not Muted
Muted
PCM
External DF
SACD Slave
SACD Master
Stereo
Not Allowed
Mono Left
Mono Right
48 kHz
96 kHz
192 kHz
Reserved
None
44.1 kHz
32 kHz
48 kHz
I2S
Right-Justified
DSP
Left-Justified
24 bits
20 bits
18 bits
16 bits
Table II. DAC Control Register 1
Bit Description
10:9 MCLK Mode
8
Zero Flag Polarity
7
SACD Bit Rate
6
SACD Mode
5:4 SACD Phase Select
3
SACD Bit Inversion
2
SACD MCLK to
BCLK Phase
1:0 SPI Register Address
Default = 0
Value
00
01
10
11
0
1
0
1
0
1
00
01
10
11
0
1
0
1
01
Definition
256 Ï« fS
512 Ï« fS
768 Ï« fS
Reserved
Active High
Active Low
64 Ï« fS
128 Ï« fS
Normal
Phase Mode
Phase 0
Phase 1
Phase 2
Phase 3
Normal
Inverted
Rising Edge
Falling Edge
Table III. DAC Volume Registers
Bit Description
15:2 Volume
1:0 SPI Register Address
Default = Full Volume
Value Definition
14-Bit
Unsigned
10
Left Volume
11
Right Volume
–14–
REV. 0