EVAL-AD1955EB Datasheet, PDF (4/24 Pages) Analog Devices – High Performance Multibit
- DAC with SACD Playback

AD1955
SPECIFICATIONS (continued)
GROUP DELAY
Chip Mode
Group Delay Calculation
INT8Ï« Mode
INT4Ï« Mode
INT2Ï« Mode
5553/(128 Ï« f_S)
5601/(64 Ï« f_S)
5659/(32 Ï« f_S)
Specifications subject to change without notice.
f_S (kHz)
48
96
192
DIGITAL TIMING (Guaranteed over –40؇C to +85؇C, AVDD = DVDD = 5.0 V ؎ 10%.)
Parameter
Description
t_DMP
t_DML
t_DMH
t_DBH
t_DBL
t_DBP
t_DLS
t_DLH
t_DWH
t_DWL
t_DDS
t_DDH
t_DPHS
t_DSDS
t_DSDH
t_DSKP
t_DSKH
t_DSKL
t_DMP
t_DML
t_DMH
t_CLS
t_CLH
t_CDS
t_CDH
t_RSTL
MCLK Period (F_MCLK = 256 Ï« F_LRCLK)
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK/EF_BCLK High
BCLK/EF_BCLK Low
BCLK/EF_BCLK Period
LRCLK/EF_WCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
EF_WCLK High
EF_WCLK Low
SDATA/EF_LDATA/EF_RDATA Setup
SDATA/EF_LDATA/EF_RDATA Hold
DSD_PHASE Setup
DSD_DATA Setup
DSD_DATA Hold
DSD_SCLK Period
DSD_SCLK High
DSD_SCLK Low
CCLK Period
CCLK LO Pulsewidth
CCLK HI Pulsewidth
CLATCH Setup
CLATCH Hold
CDATA Setup
CDATA Hold
RST LO Pulsewidth
Specifications subject to change without notice.
Group Delay
903.8
911.6
921
Min
50
0.4 Ï« t_DMP
0.4 Ï« t_DMP
20
20
60
0
15
20
20
0
20
20
5
5
60
20
20
50
15
10
0
15
0
5
10
Unit
µs
µs
µs
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–4–
REV. 0