DAC8420 Datasheet, PDF (6/16 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420
PIN CONFIGURATIONS
DIP
SOL
VDD 1
16 CLSEL
VOUTD ²
15 _CLR
VOUTC ³
VREFLO ⁴
VREFHI 5
VOUTB 6
DAC8420
TOP VIEW
(Not to Scale)
14 LD
13 NC
12 CS
11 CLK
VOUTA 7
10 SDI
VSS ⁸
9 GND
NC = NO CONNECT
VDD 1
16 CLSEL
VOUTD 2 _DAC-8420 15 _CLR
VOUTC
VREFLO
3
4
TOP VIEW 14
(DNDAoAtCtCo-88S44c2a20le0) 13
TOP VIEW
LD
NC
TOP VIEW
VREFHI ⁵
(Not to Scale) ¹² CS
(Not to Scale)
VOUTB 6
11 CLK
VOUTA 7
10 SDI
VSS 8
9 GND
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
Power Supplies
Clock
Control Inputs
Data Input
Reference Inputs
Analog Outputs
VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to –15 V.
GND: Digital Ground.
CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS.
(All are CMOS/TTL compatible.)
CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800_H). If LOW, the registers are set to zero (000_H).
CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data
must remain stable while LD is LOW.
(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST)
(LAST)
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
A1 A0 NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
—Address Word—
(MSB)
—DAC Data Word—
(LSB)
NC = Don’t Care.
VREFHI: Upper DAC ladder reference voltage input. Allowable range is (V_DD – 2.5 V) to (V_VREFLO +2.5 V).
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is V_SS to
(V_VREFHI – 2.5 V).
VOUTA through VOUTD: Four buffered DAC voltage outputs.
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