DAC8420 Datasheet, PDF (2/16 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (at V_DD = +5.0 V ؎ 5%, V_SS = 0.0 V, V_VREFHI = +2.5 V, V_VREFLD = 0.0 V, and
V_SS = –5.0 V ؎ 5%, V_VREFLO = –2.5 V, –40؇C ≤ T_A ≤ +85؇C unless otherwise noted. See Note 1 for supply variations.)
Parameter
Symbol Condition
Min
Typ
Max
STATIC ACCURACY
Integral Linearity “E”
Integral Linearity “E”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
MATCHING PERFORMANCE
Linearity Matching
REFERENCE
Positive Reference Input Range
Negative Reference Input Range
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
INL
INL
INL
INL
DNL
ZSE
FSE
ZSE
FSE
TC_ZSE
TC_FSE
Note 2, V_SS = 0 V
Note 2, V_SS = 0 V
Monotonic Over Temperature
R_L = 2 kΩ, V_SS = –5 V
R_L = 2 kΩ, V_SS = –5 V
Note 2, R_L = 2 kΩ, V_SS = 0 V
Note 2, R_L = 2 kΩ, V_SS = 0 V
Note 3, R_L = 2 kΩ, V_SS = –5 V
Note 3, R_L = 2 kΩ, V_SS = –5 V
± 1/4
±1
± 1/2
±3
± 3/4
±2
±1
±4
± 1/4
±1
±4
±4
±8
±8
± 10
± 10
±1
V_VREFHI
V_VREFLO
V_VREFLO
I_VREFHI
I_VREFLO
Note 4
Note 4
Note 4, V_SS = 0 V
Codes 000_H, 555_H
Codes 000_H, 555_H, V_SS = –5 V
V_VREFLO +2.5
V_SS
0
–0.75
–1.0
± 0.25
–0.6
V_DD –2.5
V_VREFHI –2.5
V_VREFHI –2.5
+0.75
I_OUT
V_SS = –5 V
t_S
to 0.01%, Note 5
SR
10% to 90%, Note 5
–1.25
+1.25
8
1.5
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance
V_INH
V_INL
I_IN
C_IN
Note 3
2.4
0.8
10
13
LOGIC TIMING CHARACTERISTICS^{3, 6}
Data Setup Time
t_DS
25
Data Hold
t_DH
55
Clock Pulse Width HIGH
t_CH
90
Clock Pulse Width LOW
t_CL
120
Select Time
t_CSS
90
Deselect Delay
t_CSH
5
Load Disable Time
t_LD1
130
Load Delay
t_LD2
35
Load Pulse Width
t_LDW
80
Clear Pulse Width
t_CLRW
150
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
I_DD
I_SS
P_DISS
V_SS = 0 V
0.002 0.01
4
7
–6
–3
20
35
NOTES
1_{All supplies can be varied ± 5% and operation is guaranteed. Device is tested with VDD = +4.75 V.}
2_{For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at code 003H.}
3_{Guaranteed but not tested.}
4_{Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.}
5_{VOUT swing between +2.5 V and –2.5 V with VDD = 5.0 V.}
6_{All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.}
7_{Typical values indicate performance measured at +25°C.}
Specifications subject to change without notice.
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
V
V
V
mA
mA
mA
µs
V/µs
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%/%
mA
mA
mW
–2–
REV. 0