DAC8420 Datasheet, PDF (14/16 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420
+5V SUPPLY
0.1µF
REF-43
2 VIN
+5V SUPPLY
2.5V
4 _GND V_OUT 6
VREFHI
5
1
0.1µF
VINA
+5V
0.1µF
3
CMP-04
DAC-8420
DAC A
DAC B
7
VOUTA
VOUTB
6
DIGITAL
CONTROL
DAC C
DAC D
VOUTC
3
VOUTD
2
10 11 12 14 15 16 9
4
8
GND VREFLO VSS
5
C1
2
4
7
C2
1
6
9
C3
14
8
11
C4
13
10
12
DIGITAL INPUTS
VINB
Figure 31. Dual Programmable Window Comparator
+5V
604Ω
RED LED
+5V
604Ω
OUT A
RED LED
OUT B
MC68HC11 Microcontroller Interfacing
Figure 32 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
68HC11 drives the CLK input of the DAC, and the MOSI port
outputs the serial data to load into the SDI input of the DAC.
The port lines PD5, PC0, PC1, and PC2 provide the controls to
the DAC as shown.
PC2
PC1
PC0
MC68HC11*
(PD5) SS
SCK
MOSI
CLSEL
CLR
CS
DAC-8420*
LD
CLK
SDI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 32. MC68HC11 Microcontroller Interface
For correct operation, the 68HC11 should be configured such
that its CPOL bit and CPHA bit are both set to 1. In this con-
figuration, serial data on MOSI of the 68HC11 is valid on the
rising edge of the clock, which is the required timing for the
DAC8420 Data is transmitted in 8-bit bytes (MSB first), with
only eight rising clock edges occurring in the transmit cycle. To
load data to the DAC8420’s input register, PC0 is taken low
and held low during the entire loading cycle. The first 8 bits are
shifted in address first, immediately followed by another 8 bits
in the second least-significant byte to load the complete 16-bit
word. At the end of the second byte load, PC0 is then taken
high. To prevent an additional advancing of the internal shift
register, SCK must already be asserted before PC0 is taken
high. To transfer the contents of the input shift register to the
DAC register, PD5 is then taken low, asserting the LD input of
the DAC and completing the loading process. PD5 should re-
turn high before the next load cycle begins. The DAC8420’s
CLR input, controlled by the output PC1, provides an asyn-
chronous clear function.
–14–
REV. 0