ADSP-BF561_06 Datasheet, PDF (6/60 Pages) Analog Devices – Blackfin Embedded Symmetric Multiprocessor

ADSP-BF561
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 4000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xFEB2 0000
0xFEB0 0000
0xEF00 4000
0xEF00 0000
0x3000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
Top of last SDRAM page
0x0000 0000
CORE A MEMORY MAP
CORE B MEMORY MAP
CORE MMR REGISTERS
CORE MMR REGISTERS
SYSTEM MMR REGISTERS
RESERVED
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
RESERVED
L1 INSTRUCTION SRAM (16K)
RESERVED
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
RESERVED
RESERVED
L1 INSTRUCTION SRAM (16K)
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L2 SRAM (128K)
RESERVED
BOOT ROM
RESERVED
ASYNC MEMORY BANK 3
ASYNC MEMORY BANK 2
ASYNC MEMORY BANK 1
ASYNC MEMORY BANK 0
RESERVED
SDRAM BANK 3
SDRAM BANK 2
SDRAM BANK 1
SDRAM BANK 0
Figure 3. Memory Map
0xFF80 0000
0xFF70 1000
0xFF70 0000
0xFF61 4000
0xFF61 0000
0xFF60 4000
0xFF60 0000
0xFF50 8000
0xFF50 4000
0xFF50 0000
0xFF40 8000
0xFF40 4000
0xFF40 0000
INTERNAL MEMORY
EXTERNAL MEMORY
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the frequency of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128K bytes L2 SRAM memory.
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices, including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Rev. A | Page 6 of 60 | May 2006