ADSP-BF561_06 Datasheet, PDF (33/60 Pages) Analog Devices – Blackfin Embedded Symmetric Multiprocessor

Table 25. External Late Frame Sync
Parameter
Switching Characteristics
t_DDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0^{1, 2}
t_DTENLFS Data Enable from Late FS or MCE = 1, MFD = 0^{1, 2}
1 _{MCE = 1, TFS enable and TFS valid follow tDTENLFS and t . DDTLFSE}
2 _{If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.}
Min
0
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
RSCLK
t_SFSE/I
DRIVE
t_HOFSE/I
RFS
DT
t_DTENLFS
t_DDTLFSE
1ST BIT
t_DDTE/I
t_HDTE/I
2ND BIT
LATE EXTERNAL TFS
DRIVE
SAMPLE
TSCLK
t_SFSE/I
DRIVE
t_HOFSE/I
TFS
DT
t_DTENLFS
t_DDTLFSE
1ST BIT
t_DDTE/I
t_HDTE/I
2ND BIT
Figure 18. External Late Frame Sync (Frame Sync Setup < t_SCLK/2)
ADSP-BF561
Max
Unit
10.0
ns
ns
Rev. A | Page 33 of 60 | May 2006