ADSP-BF561_06 Datasheet, PDF (1/60 Pages) Analog Devices – Blackfin Embedded Symmetric Multiprocessor

a
FEATURES
Dual symmetric 600 MHz high performance Blackfin cores
328K bytes of on-chip memory (see memory information
on Page 4)
Each Blackfin core includes:
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of program-
ming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.35 V core V_DD with on-chip voltage regulator
3.3 V and 2.5 V compliant I/O
256-ball mini-BGA and 297-ball PBGA package options
Blackfin^® Embedded
Symmetric Multiprocessor
ADSP-BF561
PERIPHERALS
Two parallel input/output peripheral interface units support-
ing ITU-R 656 video and glueless interface to analog front
end ADCs
Two dual channel, full duplex synchronous serial ports sup-
porting eight stereo I²S channels
Dual 16-channel DMA controllers and one internal memory
DMA controller
12 general-purpose 32-bit timers/counters, with PWM
capability
SPI^®-compatible port
UART with support for IrDA^®
Dual watchdog timers
48 programmable flags
On-chip phase-locked loop capable of 0.5× to 64× frequency
multiplication
IRQ CONTROL/
WATCHDOG
TIMER
VOLTAGE
REGULATOR
B
B
IRQ CONTROL/
WATCHDOG
TIMER
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L2 SRAM
128K BYTES
CORE SYSTEM/BUS INTERFACE
EAB
32
BOOT ROM
DMA
CONTROLLER1
DEB
DMA
CONTROLLER2
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI0
PPI1
IMDMA
CONTROLLER
DAB
16
PAB 16
JTAG TEST
EMULATION
UART
IrDA
SPI
SPORT0
SPORT1
GPIO
TIMERS
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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Specifications subject to change without notice. No license is granted by implication
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