AD9974BBCZ Datasheet, PDF (6/52 Pages) Analog Devices – Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core

AD9974
ANALOG SPECIFICATIONS
X = A = B, AVDD_X = 1.8 V, fCLI = 65 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
CDS¹
Allowable CCD Reset Transient
CDS Gain Accuracy
−3 dB CDS Gain
0 dB CDS Gain (Default)
3 dB CDS Gain
6 dB CDS Gain
Maximum Input Voltage
−3 dB CDS Gain
0 dB CDS Gain (Default)
3 dB CDS Gain
6 dB CDS Gain
Allowable OB Pixel Amplitude
0 dB CDS Gain (Default)
6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA_X)
Gain Control Resolution
Gain Monotonicity
Low Gain Setting (VGA Code 15, Default)
Maximum Gain Setting (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ADC (CHN_A and CHN_B)
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity (INL)
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT_X)
Reference Bottom Voltage (REFB_X)
SYSTEM PERFORMANCE
VGA Gain Accuracy
Low Gain (Code 15)
Maximum Gain (Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Min Typ
0.5
−3.3 −2.8
−0.7 −0.2
2.3 2.8
4.9 5.4
1.4
1.0
0.7
0.5
−100
−50
1024
Guaranteed
6
42
1024
0
1023
14
−1.0 ±0.5
Guaranteed
5
2.0
1.4
0.4
5.1 5.6
41.3 41.8
0.1
2
48
Max Unit
Test Conditions/Comments
0.8 V
−2.3
+0.3
3.3
5.9
V p-p
V p-p
V p-p
V p-p
VGA gain = 5.6 dB (Code 15, default value)
+200 mV
+100 mV
Steps
dB
dB
Steps
LSB
LSB
Measured at ADC output
Measured at ADC output
Bits
+1.2 LSB
15 LSB
V
V
V
Specifications include entire signal chain
0 dB CDS gain (default)
6.1 dB
Gain = (0.0359 × code) + 5.1 dB
42.3 dB
0.4 %
12 dB total gain applied
LSB rms AC-grounded input, 6 dB gain applied
dB
Measured with step change on supply
1 _{Input signal characteristics are defined as shown in Figure 2.}
Rev. A | Page 6 of 52