AD9974BBCZ Datasheet, PDF (43/52 Pages) Analog Devices – Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core

AD9974
Address
0x0C
0x0D
Data Bit
Content
[27:0]
[0]
Default
Value
0
0
Update
VD
VD
Name
TESTMODE
CLIDIVIDE
[3:1]
0
[27:4]
0x0E
[27:0]
0x0F
[27:0]
TESTMODE
Unused
SCK
Unused
SCK
Unused
Table 23. Miscellaneous Registers
Data Bit
Address Content
Default
Value
0x10
[0]
0
Update
SCK
Name
SW_RST
[27:1]
0x11
[0]
0
Unused
VD
OUT_CONTROL
[27:1]
0x12
[1:0]
0
[27:2]
0x13
[0]
0
[27:1]
0x14
[0]
0
Unused
SCK
TESTMODE
Unused
SCK
TESTMODE
Unused
SCK
TGCORE_RST
[27:1]
0x15
[0]
0
Unused
SCK
CLI_BIAS
[27:1]
0x16
[0]
0
[27:1]
0x17
[12:0]
0
[13]
0
Unused
SCK
TESTMODE
Unused
SCK
UPDATE
PREVENTUP
[27:14]
0x18
[27:0]
0
0x19
[27:0]
0
0x1A to
0x1F
[27:0]
Table 24. VD/HD Registers
Address
Data Bit
Content
Default
Value
0x20
[0]
0
[27:1]
0x21
[0]
0
Update
SCK
SCK
Unused
TESTMODE
TESTMODE
Unused
Name
TESTMODE
Unused
VDHDPOL
0x22
[2:1]
0
[27:3]
[27:0]
0
TESTMODE
Unused
TESTMODE
Description
Test Operation Only. Set to 0 if this register is accessed.
CLI Divide.
1 = divide CLI input frequency by 2.
Test Operation Only. Set to 0.
Set unused bits to 0.
Set unused register to 0 if accessed.
Set unused register to 0 if accessed.
Description
Software Reset. Bit self-clears to 0 when a reset occurs.
1 = reset Address 0x00 to Address 0xFF to default values.
Set unused bits to 0.
Output Control.
0 = make all outputs dc inactive.
1 = enable outputs at next VD edge.
Set unused bits to 0.
Test Operation Only. Set to 0.
Set unused bits to 0.
Test Operation Only. Set to 0.
Set unused bits to 0.
Timing Core Reset Bar.
0 = hold in reset.
1 = resume operation.
Set unused bits to 0.
Enable bias for CLI input (see Figure 11).
0 = disable bias (CLI input is dc-coupled).
1 = enable bias (CLI input is ac-coupled).
Set unused bits to 0.
Test Operation Only. Set to 0.
Set unused bits to 0.
Serial Interface Update Line. Sets the line (HD) within the field to
update the VD-updated registers. Disabled when PREVENTUP = 1.
Prevents normal update of VD-updated registers.
0 = normal update at VD.
1 = prevent update of VD-updated registers.
Set unused bits to 0.
Test Operation Only. Set to 0 if this register is accessed.
Test Operation Only. Set to 0 if this register is accessed.
Set unused bits to 0.
Description
Test Operation Only. Set to 0.
Set unused bits to 0.
VD/HD Active Polarity.
0 = active low.
1 = active high.
Test Operation Only. Set to 0.
Set unused bits to 0.
Test Operation Only. Set to 0 if this register is accessed.
Rev. A | Page 43 of 52