AD9974BBCZ Datasheet, PDF (1/52 Pages) Analog Devices – Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing Core

Dual-Channel, 14-Bit, CCD Signal
Processor with Precision Timing Core
AD9974
FEATURES
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with
−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package
Internal low dropout (LDO) regulator circuitry
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
GENERAL DESCRIPTION
The AD9974 is a highly integrated, dual-channel, charge-
coupled device (CCD) signal processor for high speed digital
video camera applications. Each channel is specified at pixel
rates of up to 65 MHz. The AD9974 consists of a complete
analog front end (AFE) with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timing™ core allows adjustment of high speed clocks with
approximately 240 ps resolution at 65 MHz operation.
Each AFE includes black level clamping, CDS, VGA, and
a 65 MSPS, 14-bit ADC. The timing driver provides the high
speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,
and H1_B to H4_B outputs. A 3-wire serial interface is used to
program each channel of the AD9974.
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9974 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
CCDINP_A
CCDINM_A
CCDINP_B
CCDINM_B
AD9974
VREF_A
CDS
–3, 0, +3, +6dB
–3, 0, +3, +6dB
CDS
VREF_B
VGA
6dB TO 42dB
6dB TO 42dB
VGA
ADC
CLAMP
CLAMP
ADC
14
DOUT_A
14
DOUT_B
1.8V OUTPUT
LDO A
1.8V OUTPUT
LDO B
INTERNAL CLOCKS
RG_A
RG_B
H1_A TO H4_A
H1_B TO H4_B
4
HORIZONTAL
DRIVERS
4
PRECISION
TIMING
CORE
SYNC
GENERATOR
INTERNAL
REGISTERS
CLI_A
CLI_B
SCK_A
SCK_B
HD_A VD_A HD_B VD_B
Figure 1.
SL_A SDATA_A SL_B SDATA_B
Rev. A
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