AD9549_15 Datasheet, PDF (6/76 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer

AD9549
AC SPECIFICATIONS
f_S = 1 GHz, DAC R_SET = 10 kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted.
Table 2.
Parameter
REFERENCE INPUTS
Frequency Range (Sine Wave)
Frequency Range (CMOS)
Frequency Range (LVPECL)
Frequency Range (LVDS)
Min
10
0.008
0.008
0.008
Typ Max
750
50
725
725
Minimum Slew Rate
0.04
Minimum Pulse Width High
620
Minimum Pulse Width Low
620
FDBK_IN INPUT
Input Frequency Range
10
Minimum Differential Input Level
225
Minimum Slew Rate
40
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Frequency Range
250
Duty Cycle
45
Minimum Differential Input Level
632
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
700
VCO Frequency Range, Auto Band
810
VCO Frequency Range, High Band
900
Maximum Input Rate of System Clock PFD
Without SYSCLK PLL Doubler
Input Frequency Range
11
Multiplication Range
4
Minimum Differential Input Level
632
With SYSCLK PLL Doubler
Input Frequency Range
6
Multiplication Range
8
Input Duty Cycle
Minimum Differential Input Level
632
Crystal Resonator with SYSCLK PLL Enabled
Crystal Resonator Frequency Range
10
Maximum Crystal Motional Resistance
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
20
Duty Cycle
48
Rise Time/Fall Time (20-80%)
Jitter (12 kHz to 20 MHz)
HSTL Output Driver with 2× Multiplier
Frequency Range
400
Duty Cycle
45
Rise Time/Fall Time (20% to 80%)
Subharmonic Spur Level
Jitter (12 kHz to 20 MHz)
400
1000
55
810
900
1000
200
200
66
100
132
50
50
100
725
52
115 165
1.0
725
55
115 165
−35
1.1
Unit
MHz
MHz
MHz
MHz
V/ns
ps
ps
MHz
mV p-p
V/μs
Test Conditions/Comments
Pin 12, Pin 13, Pin 15, and Pin 16
Minimum recommended slew rate: 40 V/μs
LVDS must be ac-coupled; lower frequency bound may
be higher, depending on the size of the decoupling
capacitor
Pin 40, Pin 41
−12 dBm into 50 Ω; must be ac-coupled
Pin 27, Pin 28
MHz
%
mV p-p
Maximum f_OUT is 0.4 × f_SYSCLK
0 dBm into 50 Ω
MHz
When in the range, use the low VCO band exclusively
MHz
When in the range, use the VCO Auto band select
MHz
When in the range, use the high VCO band exclusively
MHz
MHz
mV p-p
Integer multiples of 2, maximum PFD rate and system
clock frequency must be met
0 dBm into 50 Ω
MHz
%
mV p-p
Integer multiples of 8
Deviating from 50% duty cycle may adversely affect
spurious performance.
0 dBm into 50 Ω
MHz
AT cut, fundamental mode resonator
Ω
See the SYSCLK Inputs section for recommendations
MHz
See Figure 12 for maximum toggle rate
%
ps
100 Ω termination across OUT/OUTB, 2 pF load
ps
f_IN = 19.44 MHz, f_OUT = 155.52 MHz. 50 MHz system
clock input (see Figure 3 to Figure 11 for test conditions)
MHz
%
ps
100 Ω termination across OUT/OUTB, 2 pF load
dBc
Without correction
ps
f_IN = 19.44 MHz, f_OUT = 622.08 MHz, 50 MHz system
clock input (see Figure 3 to Figure 11 for test conditions)
Rev. D | Page 6 of 76