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AD9549_15 Datasheet, PDF (4/76 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer
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AD9549
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter
Min
Typ
SUPPLY VOLTAGE
DVDD_I/O (Pin 1)
3.135
3.30
DVDD (Pin 3, Pin 5, Pin 7)
1.71
1.80
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)
3.135
3.30
AVDD3 (Pin 37)
1.71
3.30
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, 1.71
1.80
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT
IAVDD3 (Pin 14)
4.7
IAVDD3 (Pin 37)
3.8
IAVDD3 (Pin 46, Pin 47, Pin 49)
26
IAVDD (Pin 36, Pin 42)
21
IAVDD (Pin 11)
IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 44, Pin 45)
IAVDD (Pin 53)
IDVDD (Pin 3, Pin 5, Pin 7)
IDVDD_I/O (Pin 1)
LOGIC INPUTS (Except Pin 32)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CLKMODESEL (Pin 32) LOGIC INPUT
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
LOGIC OUTPUTS
12
215
41
254
4
2.0
DVSS
±60
3
1.4
AVSS
−18
3
Max
3.465
1.89
3.465
3.465
1.89
5.6
4.5
29
26
15
281
49
265
6
DVDD_I/O
0.8
±200
AVDD
0.4
−50
Output High Voltage (VOH)
Output Low Voltage (VOL)
REFERENCE INPUTS
Input Capacitance
Input Resistance
Differential Operation
Common Mode Input Voltage1
(Applicable When DC-Coupled)
Differential Input Voltage Swing1
Single-Ended Operation
Input Voltage High (VIH)
Input Voltage Low (VIL)
Threshold Voltage
Input Current
FDBK_IN INPUT
Input Capacitance
Input Resistance
Differential Input Voltage Swing2
2.7
DVSS
DVDD_I/O
0.4
3
8.5
11.5
14.5
1.5
AVDD3 −
0.2
500
2.0
AVSS
AVDD3 −
0.66
AVDD3 −
0.82
AVDD3
0.8
AVDD3 −
0.98
1
3
18
22
26
225
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
µA
pF
V
V
µA
pF
V
V
pF
kΩ
V
mV p-p
V
V
V
mA
pF
kΩ
mV p-p
Test Conditions/Comments
Pin 37 is typically 3.3 V, but can be set to 1.8 V
REFA, REFB buffers
CMOS output clock driver at 3.3 V
DAC output current source, fS = 1 GSPS
FDBK_IN input, HSTL output clock driver
(output doubler turned on)
REFA and REFB input buffer 1.8 V supply
Aggregate analog supply, including system
clock PLL
DAC power supply
Digital core
Digital I/O (varies dynamically)
Pin 9, Pin 10, Pin 54 to Pin 61, Pin 63, Pin 64
At VIN = 0 V and VIN = DVDD_I/O
Pin 32 only
At VIN = 0 V and VIN = AVDD
Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
IOH = 1 mA
IOL = 1 mA
Pin 12, Pin 13, Pin 15, Pin 16
Differential at Register 0x040F[1:0] = 00
Differential operation; note that LVDS signals
must be ac-coupled
Differential operation
Register 0x040F[1:0] = 10
Register 0x040F[1:0] = 10 (other settings
possible)
Single-ended operation
Pin 40, Pin 41
Differential
−12 dBm into 50 Ω; must be ac-coupled
Rev. D | Page 4 of 76
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