AD9549_15 Datasheet, PDF(52/76 Page) Analog Devices – Dual Input Network Clock Generator/Synchronizer

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AD9549_15 Datasheet, PDF (52/76 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer

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AD9549

Addr

(Hex)

Type1 Name

Bit 7

Calibration (user-accessible trim)

0x0400

K-divider

0x0401

0x0402 M

CPFD gain

0x0403 M

0x0404

FPFD gain

0x0405

Reserved

0x0406 RO

Part

version

Part

version

0x0407

Reserved

0x0408

0x0409 M

PFD offset

0x040A M

0x040B

0x040C

DAC

full-scale

current

0x040D

Reserved

0x040E

Reserved

0x040F

Reference

bias level

0x0410

Reserved

Harmonic spur reduction

0x0500 M

Spur A

HSR-A

enable

0x0501 M

0x0502 M

0x0503 M

0x0504 M

0x0505 M

0x0506 M

0x0507 M

0x0508 M

0x0509 M

Spur B

HSR-B

enable

Bit 6

Bit 5

Bit 4

Bit 3

BIt 2

Bit 1

Bit 0

Default

(Hex)

Part

version

K-divider, Bits[15:0]

CPFD gain scale, Bits[2:0]

CPFD gain, Bits[5:0]

FPFD gain, Bits[7:0]

Reserved

0x01

0x00

0x20

0xC8

0x00 or

0x40

DPLL phase offset, Bits[7:0]

DPLL phase offset, Bits[13:8]

DAC full-scale current, Bits[7:0]

DAC full-scale current,

Bits[9:8]

Reserved

DC input level, Bits[1:0]

0x00

0xFF

0x01

0x10

0x00

Reserved

Amplitude

gain Ã 2

Amplitude

gain Ã 2

Reserved

Spur A harmonic, Bits[3:0]

Spur A magnitude, Bits[7:0]

Spur A phase, Bits[7:0]

Reserved

Spur B harmonic[3:0]

Spur A

phase,

Bit 8

Spur B magnitude, Bits[7:0]

Spur B phase, Bits[7:0]

Spur B

phase,

Bit 8

0x00

1 Types of registers: RO = read-only, AC = autoclear, M = mirrored (also called buffered). A mirrored register needs an I/O update for the new value to take effect.

Rev. D | Page 52 of 76

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