AD9549_15 Datasheet, PDF (37/76 Pages) Analog Devices – Dual Input Network Clock Generator/Synchronizer

AD9549
Single-Ended CMOS Output
In addition to the high speed differential output clock driver, the
AD9549 provides an independent, single-ended output, CMOS
clock driver. It serves as a relatively low speed (<150 MHz) clock
source. The origin of the signal generated by the CMOS clock
driver is determined by the appropriate control bits in the I/O
register map. The user can select one of two sources under
program control.
One source is the signal generated by the DDS after it has been
externally filtered and brought back on chip. In this configura-
tion, the CMOS clock driver generates the same frequency as
appears at the output of the DDS.
Note that in this configuration, the DDS output frequency must
not exceed 50 MHz.
The other source is the output of the feedback divider (S-divider).
In this configuration, the CMOS clock driver generates the same
frequency as the input reference after optional prescaling by the
R-divider (that is, fCMOS = fR/R), which is inherently limited to
a maximum of 25 MHz.
FREQUENCY SLEW LIMITER
The frequency slew limiting capability enables users to specify the
maximum rate of frequency change that appears at the output.
The function is programmable via the I/O register map. Program
control a bit to enable/disable the function (the default condition
is disable) and a register that sets the desired slew rate.
The frequency slew limiter is located between the digital loop
filter and the CCI filter, as shown in Figure 47.
The frequency slew limiter sets a boundary on the rate of change of
the output frequency of the DDS. The frequency slew limiting
constant, KSLEW, is a 48-bit value stored in the I/O register map.
The value of the constant is determined by
K _SLEW

round _{}
2 ^{48  PIO}
f_S²


δf
δt



where:
PIO is the value stored in the I/O register map for the P-divider.
fS is the DAC sample rate.
δf/δt is the desired frequency slew rate limitation.
For example, if fS = 1 GHz, PIO = 9, and δf/δt = 5 kHz/sec, then
K _SLEW

round

2 ^48
(10⁹
9
)²
⁽⁵

10³



=
721
The resulting slew rate can be calculated as
δf
δt

K _SLEW

f_S²
2 ^{48  PIO}

The preceding example yields δf/δt = 5.003 kHz/sec.
FREQUENCY ESTIMATOR
The frequency estimation function automatically sets the DDS
output frequency so that the feedback frequency (fDDS/S) and the
prescaled reference frequency (fREF_IN/R) are matched within an
error tolerance (ε0). Its primary purpose is to allow the PLL to
quickly lock when the reference frequency is not known. The error
tolerance is defined as a fractional error and is controlled by
a 16-bit programmable value (K) via the I/O register map.
The precision of any frequency measurement is dependent on
the following two factors:
 The timing resolution of the measurement device (δt)
 The duration of the measurement (Tmeas)
The frequency estimator uses fS as its measurement reference, so
δt = 1/fS (that is, δt = 1 ns for a 1 GHz DAC sample rate). The
duration of the measurement is controlled by K, which establishes
a measurement interval that is K cycles of the measured signal
such that Tmeas = KR/fREF_IN.
The frequency estimator uses a 17-bit counter to accumulate the
number of δt periods within the measurement interval. The finite
capacity of the counter puts an upper limit on the duration of the
measurement, which is constrained to Tmax = 2¹⁷/fS. If fS = 1 GHz,
this equates to ~131 μs. The fact that the measurement time is
bounded by Tmax means there is a limit to the largest value of K
(KMAX) that can be used without causing the counter to overflow.
The value of KMAX is given by
KMAX
=
floor

65,535
ρ

where:
ρ  ^fSR
f_R
R is the modulus of the feedforward divider.
fR is the input reference frequency.
REF IN ÷R
TIME
TO
DIGITAL
CONVERTER
(PHASE
DETECTOR)
DIGITAL
LOOP
FILTER
FROM “S”-DIVIDER
FREQUENCY
0
SLEW
LIMITER
1
δf/δt
CCI
FILTER
÷P
SLEW
LIMIT
VALUE
FREQUENCY
SLEW LIMIT
ENABLE
TO
DDS
Figure 47. Frequency Slew Limiter
Rev. D | Page 37 of 76
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