ADV7302A_15 Datasheet, PDF (58/68 Pages) Analog Devices – Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs

ADV7302A/ADV7303A
Appendix E
SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7302A/ADV7303A is controlled by the start active video
(SAV) and end active video (EAV) time codes in the pixel data. All
timing information is transmitted using a 4-byte synchronization
pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied high
during this mode. Blank output is available.
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
EAV CODE
Y
C
r
Y
F
F
0
0
0X
0Y
8
0
1
0
8
0
1
0
4 CLOCK
0F FAAA
0F FBBB
ANCILLARY DATA
(HANC)
268 CLOCK
SAV CODE
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
CY
b
C
r
Y
C
b
Y
C
r
Y
C
b
4 CLOCK
1440 CLOCK
4 CLOCK
END OF ACTIVE
VIDEO LINE
280 CLOCK
4 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
Figure 94. SD Slave Mode 0
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7302A/ADV7303A generates H, V, and F signals
required for the SAV and EAV time codes in the CCIR-656
standard. The H Bit is output on the S_HSYNC pin, the V Bit
is output on the S_BLANK pin, and the F Bit is output on the
S_VSYNC pin.
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
H
2
3
4
5
6
7
V
F
EVEN FIELD ^{ODD FIELD}
8
9
10
11
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
H
V
F
ODD FIELD EVEN FIELD
Figure 95. SD Master Mode 0, NTSC
–58–
283 284 285
REV. A