ADV7302A_15 Datasheet, PDF (34/68 Pages) Analog Devices – Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs

ADV7302A/ADV7303A
Table XIV. Truth Table
P_HSYNC
P_VSYNC¹
P_BLANK¹
1→0
0
0→1
1
1
0
0→1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0→1
1→0
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
NOTES
For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
1_{When Async Timing Mode is enabled, P_BLANK, Pin 25 becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.}
2_{See Figure 28.}
Reference²
a
b
c
d
e
ADV7302A/
ADV7303A
COMPOSITE
VIDEO¹
LCC1
GLL
ADV7185
VIDEO ^P19–P12
DECODER
CLKIN_A
RTC_SCR_TR
S7–S0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
RTC
H/L TRANSITION
COUNT START
4 BITS
14 BITS ^RESERVED
LOW ^RESERVED
128
13
0
21
F_SC PLL INCREMENT²
SEQUENCE
BIT³
0
RESET
BIT⁴
RESERVED
TIME SLOT 01
14
19
6768
NOT USED
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
NOTES
1_{i.e., VCR OR CABLE}
2_{FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7302A/ADV7303A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0}
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7302A/ADV7303A.
3_{PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE}
4_{RESET ADV7302A/ADV7303A DDS}
Figure 29. RTC Timing and Connections
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync Control Bit can be used for
nonstandard input video, i.e., in Fast Forward or Rewind Modes.
In Fast Forward Mode, the sync information for the start of a
new field in the incoming video usually occurs before the total
number of lines/fields are reached; in Rewind Mode, this sync
signal occurs usually after the total number of lines/fields are
reached. Conventionally, this means that the output video will
have an erroneous start of new field signals, one generated by the
incoming video and one when the internal lines/field counters
reach the end of a field. When VCR FF/RW sync control is enabled
[Subaddress 42h, Bit 5] the lines/field counters are updated
according to the incoming VSYNC signal, and the analog output
matches the incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
RESET SEQUENCE
A reset is activated with a high-to-low transition on the RESET
Pin (Pin 33) according to the timing specifications. The
ADV7302A/ADV7303A will revert to the default output con-
figuration. Figure 30 illustrates the RESET sequence timing.
RESET
DACs
OFF
VALID VIDEO
DIGITAL TIMING
PIXEL DATA
VALID
DIGITAL TIMING SIGNALS SUPPRESSED
Figure 30. RESET Timing Sequence
–34–
TIMING ACTIVE
REV. A