English
Language : 

ADSP-2196MKSTZ-160 Datasheet, PDF (54/68 Pages) Analog Devices – DSP Microcomputer
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 For current information contact Analog Devices at 800/262-5643
ADSP-2196
The PEXT equation is calculated for each class of pins that
can drive as shown in Table 24.
Table 24. PEXT Calculation
Pin Type # of Pins
% Switching
؋C
Address 15
50
MSx
1
0
WR
1
—
Data
16
50
CLKOUT 1
—
TBD pF
TBD pF
TBD pF
TBD pF
TBD pF
؋f
؋25.0 MHz
؋25.0 MHz
؋25 MHz
؋25.0 MHz
؋100 MHz
؋ VDD2
؋10.9 V
؋ 10.9 V
؋10.9 V
؋10.9 V
؋10.9 V
= PEXT
=TBD W
=TBD W
=TBD W
=TBD W
=TBD W
PEXT=TBD W
A typical power consumption can now be calculated for
these conditions by adding a typical internal power dissipa-
tion with the formula in Figure 30.
PTOTAL= PEXT + PINT
The output disable time tDIS is the difference between
tMEASURED and tDECAY as shown in Figure 32. The time
tMEASURED is the interval from when the reference signal
switches to when the output voltage decays –V from the
measured output high or output low voltage. The tDECAY is
calculated with test loads CL and IL, and with –V equal to
0.5 V.
Figure 30. PTOTAL (Typical) Calculation
Where:
• PEXT is from Table 24
• PINT is IDDINT ؋ 2.5V, using the calculation IDDINT listed in
Power Dissipation on page 52
Note that the conditions causing a worst-case PEXT are
different from those causing a worst-case PINT. Maximum
PINT cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by – V is dependent on the
capacitive load, CL and the load current, IL. This decay time
can be approximated by the equation in Figure 31.
tDECAY
=
C-----L---∆----V---
IL
Figure 31. Decay Time Calculation
5()(5(1&(
6 ,* 1$ /
W',6
92+ 0($685('
92/ 0($685('
W0 ($ 685( '
W(1$
92+ 0($685(' ± '9 9
92/ 0($685(' '9 9
W'(&$<
287387 67236
'5,9,1*
287387 67$576
'5,9,1*
+,*+,0 3('$1&( 6 7$7(
7(67 &21',7,216 &$86( 7+,692/7$*(
72 %( $3352;,0 $7(/< 9
Figure 32. Output Enable/Disable
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time tENA is the interval
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in the Output Enable/Disable diagram
(Figure 32). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
54
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.