ADSP-2196MKSTZ-160 Datasheet, PDF (44/68 Pages) Analog Devices – DSP Microcomputer

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ADSP-2196
For current information contact Analog Devices at 800/262-5643
September 2001
Serial Port (SPORT) Frame Synch Timing
Table 19 and Figure 22 describe SPORT frame synch operations.
To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3)
R/TCLK width.
Table 19. Serial Port (SPORT) Frame Synch Timing
Parameter Description
Min
Max
Unit
Switching Characteristics
t_HOFSE
t_HOFSI
t_DDTENFS
RFS Hold after RCLK (Internally Generated RFS)¹
TFS Hold after TCLK (Internally Generated TFS)¹
Data Enable from late FS or MCE = 1, MFD = 0²
t_DDTLFSE
Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 0³
t_HDTE
Transmit Data Hold after TCLK (external clk)¹
t_HDTI
Transmit Data Hold after TCLK (internal clk)¹
0
t_DDTE
Transmit Data Delay after TCLK (external clk)¹
0
t_DDTI
Transmit Data Delay after TCLK (internal clk)¹
0
Timing Requirements
t_SFSE
TFS/RFS Setup before TCLK/RCLK (external clk)³
–0.6
t_SFSI
TFS/RFS Setup before TCLK/RCLK (internal clk)³
–0.6
1_{Referenced to drive edge.}
2_{MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.}
3_{Referenced to sample edge.}
12.4
ns
12.2
ns
4.7
ns
4.7
ns
12.4
ns
12.2
ns
12.2
ns
11.1
ns
TBD
ns
TBD
ns
44
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.