ADSP-2196MKSTZ-160 Datasheet, PDF (27/68 Pages) Analog Devices – DSP Microcomputer

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September 2001 ^{For current information contact Analog Devices at 800/262-5643}
ADSP-2196
Timer PWM_OUT Cycle Timing
Table 10 and Figure 13 describe timer expired operations. The input signal is asynchronous in “width capture mode” and
has an absolute maximum input frequency of 50 MHz.
Table 10. Timer PWM_OUT Cycle Timing
Parameter Description
Min
Max
Unit
Switching Characteristic
t_HTO
Timer pulsewidth output¹
6.25
1_{The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (2}32_{–1) cycles.}
(2³²â€“1) cycles ns
+&/.
3: 0 B2 87
W₊₇₂
Figure 13. Timer PWM_OUT Cycle Timing
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
27
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.