ADSP-2196MKSTZ-160 Datasheet, PDF (51/68 Pages) Analog Devices – DSP Microcomputer

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September 2001 ^{For current information contact Analog Devices at 800/262-5643}
ADSP-2196
Table 22. JTAG Port Timing
JTAG Test And Emulation Port Timing
Table 22 and Figure 26 describe JTAG port operations.
Parameter Description
Min
Max
Unit
Switching Characteristics
t_DTDO
t_DSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low¹
Timing Parameters
4
ns
0
5
ns
t_TCK
TCK Period
20
ns
t_STAP
TDI, TMS Setup Before TCK High
4
ns
t_HTAP
t_SSYS
t_HSYS
t_TRSTW
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low²
System Inputs Hold After TCK Low²
TRST Pulsewidth³
4
ns
4
ns
5
ns
4
ns
1_{System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,}
TFS0, TFS1, RFS0, RFS1, BMS.
2_{System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,}
CLKIN, RESET.
3_{50 MHz max.}
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Figure 26. JTAG Port Timing
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
51
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.