ADSP-21161N_15 Datasheet, PDF (53/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
Parameter
Min
Max
Unit
Timing Requirements
t_TCK
TCK Period
t_CK
ns
t_STAP
TDI, TMS Setup Before TCK High
5
ns
t_HTAP
TDI, TMS Hold After TCK High
6
ns
t_SSYS
System Inputs Setup Before TCK Low¹
2
ns
t_HSYS
System Inputs Hold After TCK Low¹
15
ns
t_TRSTW
TRST Pulsewidth
Switching Characteristics
4t_CK
ns
t_DTDO
t_DSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low²
13
ns
30
ns
1 _{System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR, SBTS, ID2–0, IRQ2–0, RESET,}
BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.
2 _{System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS, CAS, SDCLK1–0, SDCKE,}
BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_DTDO
t_STAP
t_DSYS
t_HTAP
t_SSYS
Figure 33. JTAG Test Access Port and Emulation
t_HSYS
Rev. C | Page 53 of 60 | January 2013