ADSP-21161N_15 Datasheet, PDF (23/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
Clock Input
In systems that use multiprocessing or SBSRAM, CLKDBL can-
not be enabled nor can the systems use an external crystal as the
CLKIN source.
Do not use CLKOUT as the clock source for the SBSRAM
device. Using an external crystal in conjunction with CLKDBL
to generate a CLKOUT frequency is not supported. Negative
hold times can result from the potential skew between CLKIN
and CLKOUT.
Table 11. Clock Input
100 MHz
Parameter
Min
Max
Timing Requirements
t_CK
CLKIN Period¹
20
238
t_CKL CLKIN Width Low¹
7.5
119
t_CKH CLKIN Width High¹
7.5
119
t_CKRF CLKIN Rise/Fall (0.4 V–2.0 V)
3
t_CCLK CCLK Period
10
30
Switching Characteristics
t_DCKOO
t_CKOP
t_CKWH
t_CKWL
CLKOUT Delay After CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
0
t_CK –1
t_CKOP/2 – 2
t_CKOP/2 – 2
2
t_CK+1
t_CKOP/2 + 2
t_CKOP/2 + 2
1 _{CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired tCCLK.}
Min
18
7
7
9
0
t_CK –1
t_CKOP/2 – 2
t_CKOP/2 – 2
110 MHz
Max
238
119
119
3
30
2
t_CK+1
t_CKOP/2 + 2
t_CKOP/2 + 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
CLKIN
t_{DC KOO1}
CLKOUT
t_CKH
t_CKWH1
t_CKL
t_CKOP1
t_CKWL1
t_{DC KOO2}
t_CKWH2
CLKOUT
t_DCKOO2
t_{C KOP2}
t_CKWL2
NOTES:
1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING EDGE, ONLY.
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING OR FALLING EDGE.
Figure 11. Clock Input
Rev. C | Page 23 of 60 | January 2013