ADSP-21161N_15 Datasheet, PDF (4/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision float-
ing-point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the ADSP-21161N’s separate program and
data memory buses and on-chip instruction cache, the proces-
sor can simultaneously fetch four operands (two over each data
bus) and an instruction (from the cache), all in a single cycle.
CLOCK
2
3
12
LINK
DEVICES
(2 MAX)
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
ADSP-21161N
CLKIN
XTAL
CLK_CFG1-0
CLKDBL
EBOOT
BMS
LBOOT
IRQ2-0
BRST
FLAG11-0 _ADDR23-0
TIMEXP
RPBA
ID2-0
DATA47-16
RD
LXCLK
WR
LXACK
LXDAT7-0
ACK
MS3-0
SCLK0
FS0
D0A
D0B
SCLK1
FS1
D1A
D1B
RAS
CAS
DQM
SDWE
SDCLK1-0
SDCKE
SDA10
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SPI
COMPATIBLE
DEVICE
(HOST OR SLAVE)
(OPTIONAL)
SCLK2
FS2
D2A
D2B
SCLK3
FS3
D3A
D3B
CLKOUT
DMAR2-1
DMAG2-1
CS
HBR
SPICLK
SPIDS
MOSI
MISO
HBG
REDY
BR6-1
PA
SBTS
RESET RSTOUT JTAG
7
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
ADDR
DATA ^MEMORY
OE
AND
PERIPHERALS
WE _(OPTIONAL)
ACK
CS
RAS
CAS _SDRAM
DQM ^(OPTIONAL)
WE
CLK
CKE
A10
CS
ADDR
DATA
DMA DEVICE
(OPTIONAL)
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
Figure 2. System Diagram
Rev. C | Page 4 of 60 | January 2013