ADSP-21161N_15 Datasheet, PDF (46/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 30. Serial Ports — External Clock
Parameter
Timing Requirements
t_SFSE
t_HFSE
t_SDRE
t_HDRE
t_SCLKW
t_SCLK
Transmit/Receive FS Setup Before Transmit/Receive SCLK¹
Transmit/Receive FS Hold After Transmit/Receive SCLK¹
Receive Data Setup Before Receive SCLK¹
Receive Data Hold After Receive SCLK¹
SCLKx Width
SCLKx Period
1 _{Referenced to sample edge.}
Table 31. Serial Ports — Internal Clock
Parameter
Timing Requirements
t_SFSI
FS Setup Time Before SCLK (Transmit/Receive Mode)¹
t_HFSI
FS Hold After SCLK (Transmit/Receive Mode)¹
t_SDRI
Receive Data Setup Before SCLK¹
t_HDRI
Receive Data Hold After SCLK¹
1 _{Referenced to sample edge.}
Table 32. Serial Ports — External Clock
Parameter
Switching Characteristics
t_DFSE
t_HOFSE
t_DDTE
t_HDTE
FS Delay After SCLK (Internally Generated FS) ^{1, 2, 3}
FS Hold After SCLK (Internally Generated FS)^{1, 2 , 3}
Transmit Data Delay After SCLK ^{1, 2}
Transmit Data Hold After SCLK ^{1, 2}
1 _{Referenced to drive edge.}
2 _{SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.}
3 _{SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.}
Table 33. Serial Ports — Internal Clock
Parameter
Switching Characteristics
t_DFSI
t_HOFSI
t_DDTI
t_HDTI
t_SCLKIW
FS Delay After SCLK (Internally Generated FS)^{1, 2, 3}
FS Hold After SCLK (Internally Generated FS)^{1, 2, 3}
Transmit Data Delay After SCLK^{1, 2}
Transmit Data Hold After SCLK^{1, 2}
SCLK Width²
1 _{Referenced to drive edge.}
2 _{SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.}
3 _{SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.}
Min
3.5
2
1.5
4
7
2t_CCLK
Min
8
0.5t_CCLK+1
4
3
100 MHz
Min
Max
13
3
16
0
Min
–1.5
0
0.5t_SCLK–2.5
Max
Max
110 MHz
Min
Max
13
2.75
16
0
Max
4.5
7.5
0.5t_SCLK+2
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Rev. C | Page 46 of 60 | January 2013