ADSP-21477 Datasheet, PDF (52/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
Figure 33 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 46. S/PDIF Transmitter Left-Justified Mode
Parameter
Timing Requirement
t_LJD
FS to MSB Delay in Left-Justified Mode
Nominal
0
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LEFT/RIGHT CHANNEL
t_LJD
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 33. Left-Justified Mode
Unit
SCLK
Rev. B | Page 52 of 76 | March 2012